1. Field of the invention
The present invention relates to a microprocessor with an improved access time to buses.
2. Description of the related art
As is well known, a microprocessor, formed on a single semiconductor chip, usually comprises an instruction unit for producing various control signals, a register file consisting of plural registers, an operation unit and an input/output (I/O) controller.
The instruction unit includes a read-only memory (ROM), a ROM controller and a decoder. Microinstructions stored in the ROM are successively read out under the control of the ROM controller and decoded by the decoder, whereby various control signals are generated. In response to the thus generated control signals, the operation unit executes a predetermined operational processing and carries out the data communication with the register file. Data and variables necessary for the operational processing as well as a result of the operational processing are input from or output to external resources through the I/O controller. Also instructions for controlling the ROM controller are supplied, for example, from an external memory through the I/O controller.
The operating unit, the register file and the I/O controller are coupled with each other through a read bus and a write bus. In response to a write access signal from the instruction unit, data from the operation unit are stored in the register file through the write bus, and in response to a read access signal from the instruction unit, data stored in the register file are transmitted to the operation unit through the read bus. Data communication between the register file, the operation unit and external resources is carried out through the read and write buses, too.
A microprocessor is increasingly required to have higher performance. Accordingly, the number of registers of a register file may be remarkably increased. Namely, a number of registers coupled to read and write buses increases, with the result that the load capacitance of the read and write buses becomes large. This causes the prolongation of a time necessary for making access to the read or write buses.
Since output terminals of all registers of a register file and input terminals of an operation unit and an I/O controller are coupled to a read bus in parallel with each other, the load capacitance of the read bus amounts to the sum of the capacitance of wiring of the read bus, output capacity of the registers, and input capacitance of the operation unit and the I/O controller.
Among these capacity, the output capacitance of the registers becomes large with an increase of the number of the registers coupled to the read bus. Further, those capacitances are always coupled to the read bus and function as the load capacitance of the read bus, even when there is no need to make access to the registers. The same is applied to the write bus.
Therefore, even in the case where there occurs the need to make access to a read or write bus to communicate data between an operation unit and an external memory, the access time thereto is affected by the load capacitance of the read or write bus. As a result, there exists a problem that high speed access to the read or write bus becomes impossible.